Energy-Efficient Dual-Voltage Design Using Topological Constraints
نویسندگان
چکیده
منابع مشابه
Energy-Efficient Dual-Voltage Design Using Topological Constraints
We propose a method for dual supply voltage digital design to reduce energy consumption without violating the given performance requirement. Although the basic idea of placing low voltage gates on non-critical paths is well known, a new two-step procedures does it so more efficiently. First, given a circuit and its nominal single supply voltage, we find a suitable value for a lower second suppl...
متن کاملPolynomial-Time Algorithms for Designing Dual-Voltage Energy Efficient Circuits
Energy consumption of digital circuits has become a primary constraint in electronic design. The increasing popularity of the portable devices like smart phone, ipad, tablet and notebook has created an overwhelming demand for extended battery life of these devices. Numerous methods for energy reduction in CMOS circuits have been proposed in the literature. Power reduction techniques at various ...
متن کاملEfficient subgraph matching using topological node feature constraints
This paper presents techniques designed to minimise the number of states which are explored during subgraph isomorphism detection. A set of advanced topological node features, calculated from nneighbourhood graphs, is presented and shown to outperform existing features. Further, the pruning effectiveness of both the new and existing topological node features is significantly improved through th...
متن کاملDesign the Voltage Acceptability Curves for Energy Efficient Led Lamps
This paper presents the design and develops of voltage acceptability curves for LED lamps. It is done with the mathematical representation of DC bus voltage of LED lamps internal ballast circuit during voltage sags. First, experimental analysis was done to determine the effect of voltage sag of LED lamp. From the findings on the variation of DC bus voltage during voltage sag, a mathematical equ...
متن کاملEnergy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling
As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe an alternative approach, which we call a Multiple Clock Domain (MCD) processor, in which the chip is divided into several (coarse-grained) clock domains, within which independent voltage and frequenc...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Journal of Low Power Electronics
سال: 2013
ISSN: 1546-1998
DOI: 10.1166/jolpe.2013.1269